Projects/Big Ass-LED Display: Difference between revisions
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The "Big-Ass" LED displays are a pair of four 80 x 60 pixel RGBG panels (160 x 120 total subpixels) which were originally installed in the O2 Academy Leeds. These can be stacked to create a 320 x 240 subpixel display, approximately 10 ft x 10 ft across. Total power consumption varies depending on the image, but is estimated around 400 watts for the whole setup for average video content. | The "Big-Ass" LED displays are a pair of four 80 x 60 pixel RGBG panels (160 x 120 total subpixels) which were originally installed in the O2 Academy Leeds. These can be stacked to create a 320 x 240 subpixel display, approximately 10 ft x 10 ft across. Total power consumption varies depending on the image, but is estimated around 400 watts for the whole setup for average video content in the original configuration. | ||
At some point during the repair of one display module, some connectors were accidentally transposed. This led to the shorting of one of the 5V, 170A power supplies inside the units causing the destruction of modules and wiring harnessess. Phil, a member, donated them to the space after the Academy scrapped them. | At some point during the repair of one display module, some connectors were accidentally transposed. This led to the shorting of one of the 5V, 170A power supplies inside the units causing the destruction of modules and wiring harnessess. Phil, a member, donated them to the space after the Academy scrapped them. | ||
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Each panel is composed of 150 separate display modules which are essentially giant shift registers. Driving the display is not trivial. The original design uses a complex board with an FPGA, CPLD and several kilobytes of SRAM to drive just half of one panel. A control cabinet, a 4U rackmount unit, converts composite (CVBS) video into AMD TaXiCHIP format (yes, that AMD, before they focused on just making CPUs and GPUs.) This data is sent over a fibre-optic link - this is presumed to eliminate ground loops as the data rate is not that fast and coax would have been sufficient. | Each panel is composed of 150 separate display modules which are essentially giant shift registers. Driving the display is not trivial. The original design uses a complex board with an FPGA, CPLD and several kilobytes of SRAM to drive just half of one panel. A control cabinet, a 4U rackmount unit, converts composite (CVBS) video into AMD TaXiCHIP format (yes, that AMD, before they focused on just making CPUs and GPUs.) This data is sent over a fibre-optic link - this is presumed to eliminate ground loops as the data rate is not that fast and coax would have been sufficient. | ||
The 4U rackmount cab has an issue, where the 3.3V rail is low on power on. So it will not display video for about 30 minutes until it has warmed up. It will display only a blue screen for no signal, or black | The 4U rackmount cab has an issue, where the 3.3V rail is low on power on. So it will not display video for about 30 minutes until it has warmed up. It will display only a blue screen for no signal, or black when signal is input, in this state. The 3.3V LED on the front of the unit will also be visibly dimmer than the other LEDs. Once warmed up however the unit appears to work okay save for some excessive noise on the video signal though this may be due to the choice of CVBS test sources and poor, unterminated cabling. There is a basic serial terminal at 9600 baud but it has no test pattern functions or methods to load data into. The rack contains several more FPGAs and framebuffer/control ICs. It is supposed this rack sends converted, possibly gamma corrected data to the panels, which then convert it into subfields which are eventually displayed on the panel. | ||
=== Module information === | |||
Each display panel contains 150 modules, and each module is a separately addressed shift register with dedicated latch and data inputs. There are a total of 128 pixels on each module; 32 red, 32 blue and 64 green. There are four data inputs: red, green "A", blue and green "B". Note that there are twice as many green pixels as red or blue; this improves the apparent panel resolution with the large LEDs. Clock is shared; this becomes a significant limitation in terms of data rate. Each module has eight shift register chips each driving LEDs continuously, there is no multiplexing of actual output levels on the modules, which is a benefit, because it means that with some clever sub-field calculations (described later) very high brightness displays are achievable. | |||
Each module is configured into two halves, which are referred to in this documentation as the "odd half" and "even half". The modules also have a 3-bit address |
Revision as of 20:12, 17 September 2017
The "Big-Ass" LED displays are a pair of four 80 x 60 pixel RGBG panels (160 x 120 total subpixels) which were originally installed in the O2 Academy Leeds. These can be stacked to create a 320 x 240 subpixel display, approximately 10 ft x 10 ft across. Total power consumption varies depending on the image, but is estimated around 400 watts for the whole setup for average video content in the original configuration.
At some point during the repair of one display module, some connectors were accidentally transposed. This led to the shorting of one of the 5V, 170A power supplies inside the units causing the destruction of modules and wiring harnessess. Phil, a member, donated them to the space after the Academy scrapped them.
Each panel is composed of 150 separate display modules which are essentially giant shift registers. Driving the display is not trivial. The original design uses a complex board with an FPGA, CPLD and several kilobytes of SRAM to drive just half of one panel. A control cabinet, a 4U rackmount unit, converts composite (CVBS) video into AMD TaXiCHIP format (yes, that AMD, before they focused on just making CPUs and GPUs.) This data is sent over a fibre-optic link - this is presumed to eliminate ground loops as the data rate is not that fast and coax would have been sufficient.
The 4U rackmount cab has an issue, where the 3.3V rail is low on power on. So it will not display video for about 30 minutes until it has warmed up. It will display only a blue screen for no signal, or black when signal is input, in this state. The 3.3V LED on the front of the unit will also be visibly dimmer than the other LEDs. Once warmed up however the unit appears to work okay save for some excessive noise on the video signal though this may be due to the choice of CVBS test sources and poor, unterminated cabling. There is a basic serial terminal at 9600 baud but it has no test pattern functions or methods to load data into. The rack contains several more FPGAs and framebuffer/control ICs. It is supposed this rack sends converted, possibly gamma corrected data to the panels, which then convert it into subfields which are eventually displayed on the panel.
Module information
Each display panel contains 150 modules, and each module is a separately addressed shift register with dedicated latch and data inputs. There are a total of 128 pixels on each module; 32 red, 32 blue and 64 green. There are four data inputs: red, green "A", blue and green "B". Note that there are twice as many green pixels as red or blue; this improves the apparent panel resolution with the large LEDs. Clock is shared; this becomes a significant limitation in terms of data rate. Each module has eight shift register chips each driving LEDs continuously, there is no multiplexing of actual output levels on the modules, which is a benefit, because it means that with some clever sub-field calculations (described later) very high brightness displays are achievable.
Each module is configured into two halves, which are referred to in this documentation as the "odd half" and "even half". The modules also have a 3-bit address